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ds97dz80700 p r e l i m i n a r y 8-1 1 p reliminary p roduct s pecification z86c83/c84/e83 1 cmos z8 mcu features n 28-pin dip, soic, and plcc packages n clock speed: 16 mhz n three expanded register groups n 8-channel, 8-bit a/d converter with track and hold, and unique r-ladder a gnd offset control n z86c84 has two 8-bit d/a converters with programmable gain stages, 3 ? settling time n six vectored, prioritized interrupts from six different sources n two analog comparator inputs with programmable interrupt polarity n two programmable 8-bit timers, each with a 6-bit programmable prescaler n power-on reset (por) timer n permanent watch-dog timer (wdt) option n software-programmable pull-up resistors (port 2 only) n on-chip oscillator for crystal, resonator or lc n rom protect general description the z86c83/c84/e83 are full-featured members of the z8 mcu family offering a unique register-to-register ar- chitecture that avoids accumulator bottlenecks for higher code efficiency than risc processors. the z86c83/c84/e83 are designed to be used in a wide variety of embedded control applications, such as appli- ances, process controls, keyboards, security systems, bat- tery chargers, and automotive modules. for applications requiring powerful i/o capabilities, the z86c83/c84/e83 devices can have up to 21/17 (83/84 re- spectively) pins dedicated to input and output. these lines are grouped into three ports, and are configured by soft- ware to provide digital/analog i/o timing and status signals. an on-chip, half-flash 8-bit ?/2 least significant bit (lsb) a/d converter can multiplex up to eight analog inputs. un- used analog inputs revert to standard digital i/o use. unique, programmable a gnd offset control of the a/d re- sistor ladder compresses the converter's dynamic range for maximum effective 9-bit a/d resolution. the z86c84 has two 8-bit ?/2 lsb d/a converters. high and low reference voltages provide precise control of the output voltage range. programmable gain for each d/a converter provides a maximum effective 10-bit resolution for many tasks. on-chip 8-bit counter/timers with many user-selectable modes simplify real-time tasks, such as counting, timing, and generation of pwm signals. the designer can prioritize six different maskable, vec- tored, internal or external interrupts for efficient interrupt handling and multitasking functions. device rom (kb) ram* (bytes) i/o lines voltage range z86c83 4 237 21 3.0v to 5.5v Z86E83 4 (otp) 237 21 3.5v to 5.5v z86c84 4 237 17 3.0v to 5.5v note: * general-purpose
z86c83/c84/e83 cmos z8 mcu zilog 8-2 p r e l i m i n a r y ds97dz80700 general description (continued) by means of an expanded register file, the designer has access to additional control registers for configuring pe- ripheral functions including the a/d and d/a converters, counter/timers, and i/o port functions (figure 1). notes: all signals with a preceding front slash, "/", are active low. for example, b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v cc ground gnd v ss figure 1. z86c83/c84/e83 functional block diagram notes: ** not available on z86c83/e83 ? not available on z86c84 port 0 p00 p01 p02 p03? p04? p05? p06? p31 p32 p33 port 3 register file program 4k x 8 z8 core register bus internal address bus internal data bus expanded register file expanded register bus counter/timer 8-bit (2) machine timing and instruction control power xtal 1/2 vcc p34 p35 p36 ac0/p20 ac1/p21 ac2/p22 ac3/p23 ac4/p24 ac5/p25 ac6/p26 ac7/p27 port 2 comparators (2) /reset gnd 8-channel 8-bit a/d **dual 8-bit dac avcc agnd vdhi ** vdl0 ** dac1 ** dac2 ** memory
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-3 1 pin description figure 2. z86c83 and standard mode Z86E83 28-pin dip and soic pin conguration* p21/ac1 p22/ac2 p23/ac3 p24/ac4 p25/ac5 p26/ac6 p27/ac7 /reset xtal1 xtal2 gnd vcc p31 p32 p20/ac0 avcc agnd p06 p05 p04 p03 p02 p01 p00 p35 p36 p34 p33 28 z86c83/ Z86E83 dip/ soic 28 - pin 1 14 15 table 1. z86c83 and standard mode Z86E83 28-pin dip, soic, plcc pin identication* no symbol function direction 1-7 p21-p27 or ac1-ac7 port 2, bit 1-7 analog in 1-7 input/output 8 /reset reset input 9 xtal1 oscillator clock input 10 xtal2 oscillator clock output 11 gnd ground 12 v cc power 13-15 p31-p33 port 3, bits 1-3 input 16 p34 port 3, bit 4 output 17 p36 port 3, bit 6 output 18 p35 port 3, bit 5 output 19-25 p00-p06 port 0, bits 0-6 input/output 26 a gnd analog ground 27 av cc analog power 28 p20 or ac0 port 2, bit 0 analog in 0 input/output note: * dip and soic pin description and configuration are identical.
z86c83/c84/e83 cmos z8 mcu zilog 8-4 p r e l i m i n a r y ds97dz80700 pin description (continued) figure 3. z86c84 28-pin dip and soic pin conguration p21/ac1 p22/ac2 p23/ac3 p24/ac4 p25/ac5 p26/ac6 p27/ac7 /reset xtal1 xtal2 gnd vcc p31 p32 p20/ac0 avcc agnd dac1 dac2 vdhi vdlo p02 p01 p00 p35 p36 p34 p33 28 z86c84 dip/soic 28 - pin 1 14 15 table 2. z86c84 28-pin dip, soic, plcc pin identication* no symbol function direction 1-7 p21-p27 or ac1-ac7 port 2, bit 1-7 analog in 1-7 input/output 8 /reset reset input 9 xtal1 oscillator clock input 10 xtal2 oscillator clock output 11 gnd ground 12 v cc power 13-15 p31-p33 port 3, bits 1-3 input 16 p34 port 3, bit 4 output 17 p36 port 3, bit 6 output 18 p35 port 3, bit 5 output 19-21 p00-p02 port 0, bits 0-3 input/output 22 vdlo d/a ref. volt.,low input 23 vdhi d/a ref. volt.,high input 24-25 dac2-1 d/a converter output 26 a gnd analog ground 27 av cc analog power 28 p20 or ac0 port 2, bit 0 analog in 0 input/output note: * dip, plcc and soic pin description and configuration are identical
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-5 1 figure 4. Z86E83 eprom programing mode 28-pin dip and soic pin conguration d1 d2 d3 d4 d5 d6 d7 nc /ce nc gnd vcc /oe epm d0 nc nc nc nc nc nc /pgm clk clr nc nc nc vpp 28 Z86E83 (eprom mode) dip/soic 28 - pin 1 14 15 table 3. Z86E83 eprom programming mode 28-pin dip, plcc and soic pin identication no symbol function direction 1-7 d1-d7 data 1,2,3,4,5,6,7 input/output 8 nc no connection 9 /ce chip enable input 10 nc no connection 11 gnd ground 12 v cc power 13 /oe output enable input 14 epm eprom program mode input 15 v pp program voltage input 16-18 nc no connection 19 clr clear clock input 20 clk address input 21 /pgm program mode input 22-27 nc no connection 28 d0 data 0 input/output
z86c83/c84/e83 cmos z8 mcu zilog 8-6 p r e l i m i n a r y ds97dz80700 figure 5. z86c83 and standard mode Z86E83 28-pin plcc pin conguration 25 19 5 11 18 12 26 4 z86c83/e83 plcc 28 - pin 1 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx p06 p05 p04 p03 p02 p01 p00 p25/ac5 p26/ac6 p27/ac7 /reset xtal1 xtal2 gnd
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-7 1 figure 7. Z86E83 eprom programming mode 28-pin plcc pin conguration 25 19 5 11 18 12 26 4 Z86E83 plcc 28 - pin 1 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx nc nc nc nc /pgm clk clr d5 d6 d7 nc /ce nc gnd
z86c83/c84/e83 cmos z8 mcu zilog 8-8 p r e l i m i n a r y ds97dz80700 absolute maximum rating notice: stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these speci- fications is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. total power dissipation should not exceed 770 mw for the pack- age. power dissipation is calculated as follows: parameter min max units notes ambient temperature under bias ?0 +105 c storage temperature ?5 +150 c voltage on any pin with respect to v ss ?.6 +7 v 1 voltage on v cc pin with respect to v ss ?.3 +7 v voltage on /reset pin with respect to v ss ?.6 v cc +1 v 2 voltage on p32, p33 and /reset pin with respect to v ss -0.6 v cc +1 v 2,5 total power dissipation 770 mw maximum current out of v ss 140 ma maximum current into v cc 125 ma maximum current into an input pin ?00 +600 ? 3 maximum current into an open-drain pin ?00 +600 ? 4 maximum output current sinked by any i/o pin 25 ma maximum output current sourced by any i/o pin 25 ma notes: 1. this applies to all pins except /reset pin and where otherwise noted. 2. there is no input protection diode from pin to v cc . 3. this excludes xtal pins. 4. device pin is not at an output low state. 5. for Z86E83 only total power dissipation = v cc x [i cc ?(sum of i oh )] + sum of [(v cc ?v oh ) x i oh ] + sum of (v 0l x i 0l )
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-9 1 standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground. positive current flows into the referenced pin (figure 8). v dd specification v dd = 3.5v to 5.5v (Z86E83 only at 0?c to 70?c) v dd = 3.0v to 5.5v (z86c83/c84) v dd = 4.5v to 5.5v (Z86E83 only at -40?c to 105?c) capacitance t a = 25?, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. figure 8. test load diagram from output under test 150 pf i parameter min max input capacitance 0 15 pf output capacitance 0 15 pf i/o capacitance 0 15 pf
z86c83/c84/e83 cmos z8 mcu zilog 8-10 p r e l i m i n a r y ds97dz80700 dc electrical characteristics for z86c83/c84 only sym parameter v cc note 3 t a = 0?c to +70? t a = ?0? to +105? typical [13] @ 25? units conditions notes min max min max v ch clock input high voltage 3.0v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 1.3 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 3.0v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 0.7 v driven by external clock generator 5.5v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 1.5 v driven by external clock generator v ih input high voltage 3.0v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 1.3 v 5.5v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 2.5 v v il input low voltage 3.0v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 0.7 v 5.5v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 1.5 v v oh1 output high voltage 3.0v v cc -0.4 v cc -0.4 3.1 v i oh = -2.0 ma 8 5.5v v cc -0.4 v cc -0.4 4.8 v i oh = -2.0 ma 8 v ol1 output low voltage 3.0v 0.6 0.6 0.2 v i ol = +4.0 ma 8 5.5v 0.4 0.4 0.1 v i ol = +4.0 ma 8 v ol2 output low voltage 3.0v 1.2 1.2 0.3 v i ol = +6 ma 8 5.5v 1.2 1.2 0.3 v i ol = +10 ma 8 v rh reset input high voltage 3.0v .8 v cc v cc .8 v cc v cc 1.5 v 5.5v .8 v cc v cc .8 v cc v cc 2.1 v v rl reset input low voltage 3.0v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 1.1 v 5.5v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 1.7 v v offset comparator input offset voltage 3.0v 25 25 10 mv 10 5.5v 25 25 10 mv 10 i il input leakage 3.0v -1 1 -1 2 <1 ? v in = 0v, v cc 5.5v -1 1 -1 2 <1 ? v in = 0v, v cc i ol output leakage 3.0v -1 1 -1 2 <1 ? v in = 0v, v cc 5.5v -1 1 -1 2 <1 ? v in = 0v, v cc i ir reset input current 3.0v -130 -130 -25 ? 5.5v -180 -180 -40 ? i cc supply current 3.0v 20 20 7 ma @ 16 mhz 1,4 5.5v 25 25 20 ma @ 16 mhz 1,4 5.0v 7 7 3 ma @ 3.58 mhz 1,4,15 5.5v 10 10 5 ma @ 8 mhz 1,4,15
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-11 1 i cc1 standby current (halt mode) 3.0v 4.5 4.5 2.0 ma v in = 0v, v cc @ 16 mhz 4 5.5v 8 8 3.7 ma v in = 0v, v cc @ 16 mhz 4 3.0v 3.4 3.4 1.5 ma clock divide-by-16 @ 16 mhz 4 5.5v 7.0 7.0 2.9 ma clock divide-by-16 @ 16 mhz 4 i cc2 standby current (stop mode) 3.0v 8 15 1 ? v in = 0v,v cc vcc wdt is not running 1,6,11 5.5v 10 20 2 ? v in = 0v, v cc wdt is not running 1,6,11 3.0v 500 600 310 ? v in = 0v, v cc wdt is running 1,6,11,14 5.5v 800 1000 600 ? v in = 0v, v cc wdt is not running 1,6,11,14 v icr input common mode 3.0 0 v cc - 1.0v 0 v cc - 1.5v v 10 voltage range 5.5 0 v cc - 1.0v 0 v cc - 1.5v v 10 i all auto latch low current 3.0v 8 10 5 ? 0v < v in < v cc 9 5.5v 15 20 11 ? 0v < v in < v cc 9 i alh auto latch high current 3.0v -5 -7 -3 ? 0v < v in < v cc 9 5.5v -8 -10 -6 ? 0v < v in < v cc 9 v lv v cc low-voltage protection voltage 2.0 3.3 2.2 3.5 3.0 v 2 mhz max int. clk freq. 7 notes: 1. combined digital v cc and analog av cc supply currents. 2. gnd = 0v. 3. v cc voltage specification of 3.0v guarantees 3.3v ?.3v, and v cc voltage specification of 5.5v guarantees 5.0v ?.5v. 4. all outputs unloaded, i/o pins floating, inputs at rail. 5. cl1 = cl2 = 22 pf. 6. same as note [4] except inputs at v cc . 7. the v lv increases as the temperature decreases. 8. standard mode (not low emi). 9. auto latch (mask option) selected. 10. for analog comparator, inputs when analog comparators are enabled. 11. clock must be forced low, when xtal 1 is clock-driven and xtal2 is floating. 12. excludes clock pins. 13. typicals are at v cc = 5.0v and 3.3v. 14. internal rc selected 15. for z86c83 only sym parameter v cc note 3 t a = 0?c to +70? t a = ?0? to +105? typical [13] @ 25? units conditions notes min max min max
z86c83/c84/e83 cmos z8 mcu zilog 8-12 p r e l i m i n a r y ds97dz80700 ac electrical characteristics for z86c83/c84 only. low emi mode only. t a = 0? to +70? t a = -40?to +105? 4 mhz 4 mhz no symbol parameter v cc [6] min max min max units notes 1 tpc input clock period 3.0v 250 dc 250 dc ns 1,7,8 5.5v 250 dc 250 dc ns 1,7,8 2 trc, tfc clock input rise & fall times 3.0v 25 25 ns 1,7,8 5.5v 25 25 ns 1,7,8 3 twc input clock width 3.0v 125 125 ns 1,7,8 5.5v 125 125 ns 1,7,8 4 twtinl timer input low width 3.0v 100 100 ns 1,7,8 5.5v 100 100 ns 1,7,8 5 twtinh timer input high width 3.0v 3tpc 3tpc ns 1,7,8 5.5v 3tpc 3tpc ns 1,7,8 6 tptin timer input period 3.0v 4tpc 4tpc 1,7,8 5.5v 4tpc 4tpc 1,7,8 7 trtin, tftin timer input rise & fall timer 3.0v 100 100 ns 1,7,8 5.5v 100 100 ns 1,7,8 8a twil int. request low time 3.0v 100 100 ns 1,7,8 5.5v 70 70 ns 1,7,8 8b twil int. request low time 3.0v 3tpc 3tpc ns 1,3,7,8 5.5v 3tpc 3tpc ns 1,3,7,8 9 twih int. request input high time 3.0v 3tpc 3tpc ns 1,2,7,8 5.5v 3tpc 3tpc ns 1,2,7,8 10 twsm stop-mode recovery width spec 3.0v 12 12 ns 4,8 5.5v 12 12 ns 4,8 11 tost oscillator start-up time 3.0v 5tpc 5tpc 4,8,9 5.5v 5tpc 5tpc 4,8,9 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p33-p31) 3. interrupt request via port 3 (p30) 4. smr-d5 = 1, por stop mode delay is on. 5. reg. wdtmr 6. the v cc voltage specification of 3.0v guarantees 3.3v ?0.3v, and the v cc voltage specification of 5.5v guarantees 5.0v ?0.5v. 7. smr d1 = 0 8. maximum frequency for internal system clock is 4 mhz when using xtal divide-by-one mode 9. for lc oscillator and for oscillator driven by clock driver
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-13 1 for Z86E83 only t a = 0?c t a = -40?c typical to +70?c to +105?c [13] sym parameter v cc [3] min max min max @25? units conditions notes v ch clock input high voltage 3.5v 0.7 v cc v cc +0.3 1.3 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 3.5v gnd-0.3 0.2 v cc 0.7 v driven by external clock generator 5.5v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 1.5 v driven by external clock generator v ih input high voltage 3.5v 0.7 v cc v cc +0.3 1.3 v 5.5v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 2.5 v v il input low voltage 3.5v gnd-0.3 0.2 v cc 0.7 v 5.5v gnd-0.3 0.2 v cc gnd-0.3 0.2 v cc 1.5 v v oh1 ouput high voltage 3.5v v cc -0.4 3.1 v i oh = -2.0 ma 8 5.5v v cc -0.4 v cc -0.4 4.8 v i oh = -2.0 ma 8 v ol1 output low voltage 3.5v 0.6 0.2 v i oh = +4.0 ma 8 5.5v 0.4 0.4 0.1 v i oh = +4.0 ma 8 v ol2 output low voltage 3.5v 1.2 0.3 v i oh = +6.0 ma 8 5.5v 1.2 1.2 0.3 v i oh = +10.0 ma 8 v rh reset input high voltage 3.5v 0.8v cc v cc 1.5 v 5.5v 0.8v cc v cc 0.8v cc v cc 2.1 v 3.5v gnd-0.3 0.2v cc 1.1 v 5.5v gnd-0.3 0.2v cc gnd-0.3 0.2v cc 1.7 v v offs et comparator input offset voltage 3.5v 25 10 mv 10 5.5v 25 25 10 mv 10 i il input leakage 3.5v -1 1 <1 ? v in = 0v, v cc 5.5v -1 1 -1 2 <1 ? v in = 0v, v cc i ol output leakage 3.5v -1 1 <1 ? v in = 0v, v cc 5.5v -1 1 -1 2 <1 ? v in = 0v, v cc i ir reset input current 3.5v -130 -25 ? 5.5v -180 -180 -40 ? i cc supply current 3.5v 20 7 ma @16 mhz 1,4 5.5v 25 25 20 ma @16 mhz 1,4 i cc1 standby current (halt mode) 3.5v 4.5 2.0 ma v in = 0v, v cc @ 16 mhz 1,4 5.5v 8 8 3.7 ma v in = 0v, v cc @ 16 mhz 1,4 3.5v 3.4 1.5 ma clock divide by 16 @ 16 mhz 1,4 5.5v 7.0 7.0 2.9 ma clock divide by 16 @ 16 mhz 1,4
z86c83/c84/e83 cmos z8 mcu zilog 8-14 p r e l i m i n a r y ds97dz80700 i cc2 standby current (stop mode) 3.5v 8 1 ? v in = 0v, v cc wdt is not running 1,6,11 5.5v 10 20 2 ? v in = 0v, v cc wdt is not running 1,6,11 3.5v 500 310 ? v in = 0v, v cc wdt is running 1,6,11, 14 5.5v 800 1000 600 ? v in = 0v, v cc wdt is running 1,6,11, 14 v icr input common mode 3.5v 0 v cc - 1.0v 0 v 10 5.5v 0 v cc - 1.0v 0 v cc -1.5v v 10 i all auto latch low current 3.5v 8 5 ? 0v z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-15 1 ac electrical characteristics additional timing diagram figure 9. additional timing clock 1 3 4 8 2 2 3 t in irq n 6 5 7 7 11 clock setup 10 9 stop-mode recovery source
z86c83/c84/e83 cmos z8 mcu zilog 8-16 p r e l i m i n a r y ds97dz80700 ac electrical characteristics additional timing table (sclk/tclk = xtal/2) for Z86E83 only no symbol parameter v cc note 6 t a = 0? to +70? units notes 12 mhz 16 mhz min max min max 1 tpc input clock period 3.5v 83 dc 62.5 dc ns 1 5.5v 83 dc 62.5 dc ns 1 2 trc,tfc clock input rise & fall times 3.5v 15 15 ns 1 5.5v 15 15 ns 1 3 twc input clock width 3.5v 41 31 ms 1 5.5v 41 31 ns 1 4 twtinl timer input low width 3.5v 100 100 ms 1 5.5v 70 70 ns 1 5 twtinh timer input high width 3.5v 5tpc 5tpc 1 5.5v 5tpc 5tpc 1 6 tptin timer input period 3.5v 8tpc 8tpc 1 5.5v 8tpc 8tpc 1 7 trtin, timer input rise & fall timer 3.5v 100 100 ns 1 tftin 5.5v 100 100 ns 1 8a twil int. request low time 3.5v 100 100 ns 1,2 5.5v 70 70 ns 1,2 8b twil int. request low time 3.5v 5tpc 5tpc 1,3 5.5v 5tpc 5tpc 1,3 9 twih int. request input high time 3.5v 5tpc 5tpc 1,2 5.5v 5tpc 5tpc 1,2 10 twsm stop-mode recovery width spec 3.5v 12 12 ns 5.5v 12 12 ns 11 tost oscillator start-up time 3.5v 5tpc 5tpc 4 5.5v 5tpc 5tpc 4 12 twdt watch-dog timer delay time wdtmr reg d1,d0 5.5v 6.25 6.25 ms 0,0,[7] 5.5v 12.5 12.5 ms 0,1,[7] 5.5v 25 25 ms 1,0,[7] 5.5v 100 100 ms 1,1,[7] 13 t por power on reset delay 3.5v 7 24 7 25 ms 7 5.5v 3 13 3 14 ms 7 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33). 3. interrupt request via port 3 (p30). 4. smr-d5 = 0. 5. reg. wdtmr. 6. the v cc voltage specification of 3.5v guarantees 3.5v, and the v cc voltage specification of 5.5v guarantees 5.0v ?.5v. 7. using internal on-board rc oscillator.
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-17 1 ac electrical characteristics additional timing table (low emi mode only) for Z86E83 only no symbol parameter v cc [note 6] t a = 0? to +70? t a = -40? to +105? units notes 4 mhz 4 mhz min max min max 1 tpc input clock period 3.5v 250 dc ns 1,7,8 5.5v 250 dc 250 dc ns 1,7,8 2 trc,tfc clock input rise & fall times 3.5v 25 ns 1,7,8 5.5v 25 25 ns 1,7,8 3 twc input clock width 3.5v 125 ns 1,7,8 5.5v 125 125 ns 1,7,8 4 twtinl timer input low width 3.5v 100 ns 1,7,8 5.5v 70 70 ns 1,7,8 5 twtinh timer input high width 3.5v 3tpc 1,7,8 5.5v 3tpc 3tpc 1,7,8 6 tptin timer input period 3.5v 4tpc 1,7,8 5.5v 4tpc 4tpc 1,7,8 7 trtin, timer input rise & fall timer 3.5v 100 ns 1,7,8 tftin 5.5v 100 100 ns 1,7,8 8a twil int. request low time 3.5v 100 ns 1,2,7,8 5.5v 70 70 ns 1,2,7,8 8b twil int. request low time 3.5v 3tpc 1,3,7,8 5.5v 3tpc 3tpc 1,3,7,8 9 twih int. request input high time 3.5v 3tpc 1,2,7,8 5.5v 3tpc 2tpc 1,2,7,8 10 twsm stop-mode recovery width spec 3.5v 12 ns 4,8 5.5v 12 12 ns 4,8 11 tost oscillator start-up time 3.5v 5tpc 4,8,9 5.5v 5tpc 5tpc 4,8,9 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33) 3. interrupt request via port 3 (p30) 4. smr-d5 = 1, por stop mode delay is on. 5. reg. wdtmr 6. the v cc voltage specification of 3.5v guarantees 3.5v, and the v cc voltage specification of 5.5v guarantees 5.0v ?.5v. 7. smr d1 = 0 8. maximum frequency for internal system clock is 4 mhz when using xtal divide-by-one mode. 9. for lc oscillator and for oscillator driven by clock driver
z86c83/c84/e83 cmos z8 mcu zilog 8-18 p r e l i m i n a r y ds97dz80700 capacitance (continued) additional timing table (sklk/tclk = xtal/2) for z86c83/c84 only t a = 0? to +70? t a = -40? to +150? vcc 12 mhz 16mhz 12 mhz 16 mhz no sym parameter [6] min max min max min max min max units notes 1 tpc input clock period 3.0v 83 dc 62.5 dc 83 dc 62.5 dc ns 1 5.5v 83 dc 62.5 dc 83 dc 62.5 dc ns 1 2 trc, tfc clock input rise & fall times 3.0v 15 15 15 15 ns 1 5.5v 15 15 15 15 ns 1 3 twc input clock width 3.0v 41 31 41 31 ns 1 5.5v 41 31 41 31 ns 1 4 twtinl timer input low width 3.0v 100 100 100 100 ns 1 5.5v 70 70 70 70 ns 1 5 twtinh timer input high width 3.0v 5tpc 5tpc 5tpc 5tpc 1 5.5v 5tpc 5tpc 5tpc 5tpc 1 6 tptin timer input period 3.0v 8tpc 8tpc 8tpc 8tpc 1 5.5v 8tpc 8tpc 8tpc 8tpc 1 7 trtin, tftin timer input rise & fall timer 3.0v 100 100 100 100 ns 1 5.5v 100 100 100 100 ns 1 8a twil int. request low time 3.0v 100 100 100 100 ns 1,2 5.5v 70 70 70 70 ns 1,2 8b twil int. request low time 3.0v 5tpc 5tpc 5tpc 5tpc 1,3 5.5v 5tpc 5tpc 5tpc 5tpc 1,3 9 twih int. request high time 3.0v 5tpc 5tpc 5tpc 5tpc 1,2 5.5v 5tpc 5tpc 5tpc 5tpc 1,2 10 twsm stop-mode recovery width spec 3.0v 12 12 12 12 ns 5.5v 12 12 12 12 ns 11 tost oscillator start-up time 3.0v 5tpc 5tpc 5tpc 5tpc 5.5v 5tpc 5tpc 5tpc 5tpc 12 twdt watch-dog timer delay time wdtmr reg d1,d0 5.5v 6.25 6.25 6.25 6.25 ms 0,0 [6] 5.5v 12.5 12.5 12.5 12.5 ms 0,1 [6] 5.5v 25 25 25 25 ms 1,0 [6] 5.5v 100 100 100 100 ms 1,1 [6] 13 t por power on reset delay 3.0v 7 24 7 25 7 24 7 25 ms 6 5.5v 3 13 3 14 3 13 3 14 ms 6 notes: 1. timing references used 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33) 3. interrupt request via port 3 (p30) 4. smr-d5 = 0 5. the v cc voltage specification of 3.0v guarantees 3.3v?0.3v, and the v cc voltage specification of 5.5v guarantees 5.0v ?.5v. 6. using internal on-board rc oscillator
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-19 1 for z86c84 only for z86c84 only table 4. d/a converter electrical characteristics v cc = 3.3v ?10% parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.25 1 lsb differential non-linearity 0.25 0.5 lsb setting time, 1/2 lsb 1.5 3.0 ?ec zero error at 25? 10 20 mv full scale error at 25? 0.25 0.5 lsb supply range 3.0 3.3 3.6 volts power dissipation, no load 10 mw ref input resistance 2k 4k 10k ohms output noise voltage 50 ?p-p vdhi range at 3 volts 1.5 1.8 2.1 volts vdlo range at 3 volts 0.2 0.5 0.8 volts vdhi?dlo, at 3 volts 1.3 1.6 1.9 volts capacitive output load, cl 20 pf resistive output load, rl 50k ohms output slew rate 1.0 3.0 v/?ec notes: voltage: 3.0v ?3.6v temp: 0?0? table 5. d/a converter electrical characteristics v cc = 5.0v ?0% parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.25 1 lsb differential non-linearity 0.25 0.5 lsb setting time, 1/2 lsb 1.5 3.0? ?ec zero error at 25? 10 20 mv full scale error at 25? 1 2 % fsr supply range 4.5 5.0 5.5 volts power dissipation, no load 50 85 mw ref input resistance 2k 4k 10k ohms output noise voltage 50 ?p-p vdhi range at 5 volts 2.6 3.5 volts vdlo range at 5v volts 0.8 1.7 volts vdhi?dlo, at 5v volts 0.9 2.7 volts capacitive output load, cl 30 pf resistive output load, rl 20k ohms output slew rate 1.0 3.0 v/?ec notes: voltage: 4.5v - 5.5v temp: 0-70? ? the c86c84 emulator has maximum setting time of 20 ?ec. (10 ?ec. typical).
z86c83/c84/e83 cmos z8 mcu zilog 8-20 p r e l i m i n a r y ds97dz80700 capacitance (continued) for z86c83/c84 for z86c83/c84 table 6. a/d converter electrical characteristics v cc = 3.3v ?10% parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.5 1 lsb differential non-linearity 0.5 1 lsb zero error at 25? 5.0 mv supply range 2.7 3.0 3.3 volts power dissipation, no load 20 40 mw clock frequency 16 mhz input voltage range va lo va hi volts conversion time 35 x sclk ?ec input capacitance on ana 25 40 pf va hi range va lo +2.5 av cc volts va lo range an gnd av cc ?.5 volts va hi -?a lo 2.5 av cc volts notes: voltage: 3.0v ?3.6v temp: 0-70? conversion time is defined as the time from initiation of a-d conversion to storage of the digital result in the adr register. sclk = internal z8 system clock (bus speed) table 7. a/d converter electrical characteristics v cc = 5.0v ?0% parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.5 1 lsb differential non-linearity 0.5 1 lsb zero error at 25? 45 mv supply range 4.5 5.0 5.5 volts power dissipation, no load 50 85 mw clock frequency 16 mhz input voltage range va lo va hi volts conversion time 35 x sclk ?ec input capacitance on ana 25 40 pf va hi range va lo +2.5 av cc volts va lo range an gnd av cc ?.5 volts va hi -?a lo 2.5 av cc volts notes: voltage: 4.5v ?.5v temp: 0-70? conversion time is defined as the time from initiation of a-d conversion to storage of the digital result in the adr register. sclk = internal z8 system clock (bus speed)
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-21 1 for Z86E83 for Z86E83 table 8. a/d converter electrical characteristics v cc = 3.5v parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.5 1 lsb differential non-linearity 0.5 1 lsb zero error at 25? 5.0 mv supply range 3.5 volts power dissipation, no load 20 40 mw clock frequency 16 mhz input voltage range va lo va hi volts conversion time 35 x sclk ?ec input capacitance on ana 25 40 pf va hi range va lo +2.5 av cc volts va lo range an gnd av cc ?.5 volts va hi -?a lo 2.5 av cc volts notes: voltage: 3.5v temp: 0-70? conversion time is defined as the time from initiation of a-d conversion to storage of the digital result in the adr register. sclk = internal z8 system clock (bus speed) table 9. a/d converter electrical characteristics v cc = 5.0v ?0% parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.5 1 lsb differential non-linearity 0.5 1 lsb zero error at 25? 45 mv supply range 4.5 5.0 5.5 volts power dissipation, no load 50 85 mw clock frequency 16 mhz input voltage range va lo va hi volts conversion time 4.3 35 x sclk ?ec input capacitance on ana 25 40 pf va hi range va lo +2.5 av cc volts va lo range an gnd av cc ?.5 volts va hi -?a lo 2.5 av cc volts notes: voltage: 4.5v ?.5v temp: 0-70? conversion time is defined as the time from initiation of a-d conversion to storage of the digital result in the adr register. sclk = internal z8 system clock (bus speed)
z86c83/c84/e83 cmos z8 mcu zilog 8-22 p r e l i m i n a r y ds97dz80700 pin functions eprom programming mode (e83 only) d7-d0. data bus. the data can be read from or written to the eprom through the data bus. clock. address clock. this pin is a clock input. the inter- nal address counter increases by one with one clock sig- nal. clear. clear. (active high). this pin resets the internal ad- dress counter at the high level. v cc. power supply. this pin must supply 5v during the eprom read mode and 6v during other modes. /ce. chip enable (active low). this pin is active during eprom read, program, and program verify modes. /oe. output enable (active low). this pin drives the direc- tion of the data bus. when this pin is low, the data bus is output, when high, the data bus is input. epm. eprom program mode. this pin controls the differ- ent eprom program mode by applying different voltages. v pp. program voltage. this pin supplies the program volt- age. /pgm. program mode (active low). when this pin is low, the data is programmed to the eprom through the data bus. application precaution the production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above v cc occur on the /reset pin. processor operation of z8 otp devices may be affected by excessive noise surges on the vpp, /epm, /oe pins while the microcontroller is in standard mode. recommendations for dampening voltage surges in both test and otp mode include the following: n using a clamping diode to /reset, vpp, /epm, /oe n adding a capacitor to the affected pin z86c83, z86c84, and standard mode Z86E83 xtal1. crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc network or an external single-phase clock to the on-chip oscillator input. xtal2. crystal 2 (time-based output). this pin connects a parallel-resonant crystal, ceramic resonator, lc network to the on-chip oscillator output. port 0 p00-p06 (p03-p06 is not available on the z86c84). port 0 is a 7-bit, bidirectional, cmos-compatible i/o port. these seven i/o lines can be nibble programmable as p00-p03 input/output and p04-p06 input/output, separate- ly (figure 10). all input buffers are schmitt-triggered and output drivers are push-pull. port 0 auto latch. (p03-p06 has the auto latches per- manently enabled). the auto latch provides valid cmos levels when p03-p06 are selected as inputs and not ex- ternally driven. it is impossible to determine if a non-driven input is 1 or 0, however; the auto latch will sense the input condition and drive a valid cmos level, thereby eliminat- ing a floating mode that could cause excessive current.
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-23 1 figure 10. port 0 conguration r 500 k w /oen out in 1.5 2.3 hysteresis pad port 0 (i/o) notes: auto latch c83/e83: p03-p06 permanent
z86c83/c84/e83 cmos z8 mcu zilog 8-24 p r e l i m i n a r y ds97dz80700 pin functions (continued) port 2 (p27-p20) port 2 is an 8-bit, bidirectional, cmos- compatible i/o port and an 8-channel muxed input to the 8-bit adc. when configured as a digital input, by program- ming the port2 mode register, the port 2 register can be evaluated to read digital data applied to port 2, or the adc result register can be read to evaluate the analog signals applied to port 2 after configuring the adc control regis- ters. the direction of each of the eight port 2 i/o lines can be configured individually (figure 11). in addition, all four versions of the device provide the ca- pability of connecting 10k (?0%) pull-up resistors to each of the port 2 i/o lines individually. the pull-ups are con- nected when activated through software control of p2res register (figure 67) when the corresponding port 2 pin is configured to be an input. the pull-up resistor of a port 2 i/o line is automatically disabled when the corresponding i/o is an output, regardless of the state of the correspond- ing p2res bit value. note: the z86c83/c84 emulator does not emulate the p2res register. selection of the pull-ups are done via jumper settings on the emulator. figure 11. port 2 conguration port 2 (i/o) p27 p26 p25 p24 p23 p22 p21 p20 p2 analog mux select from p2res adc0 (bits 7, 6, 5) input_en /oen data adc 10k pad
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-25 1 port 3 (p36-p31) port 3 is a 6-bit, cmos-compatible port, with three fixed inputs (p33-p31) and three fixed outputs (p34-p36), configured under software control for in- put/output, counter/timers, interrupt, and port hand- shake. p31, p32, and p33 are standard cmos inputs (no auto latches). pins p34, p35, and p36 are push-pull out- put lines (figure 11). low emi output buffers can be glo- bally programmed by the software. two on-board comparators can process analog signals on p31 and p32 with reference to the voltage on p33. the an- alog function is enabled by programming port 3 mode register (p3m bit 1). for interrupt functions, port 3, pin 3 is falling-edge interrupt input. p31 and p32 are program- mable as rising, falling, or both edge triggered interrupts (irq register bits 6 and bit 7). p33 is the comparator refer- ence voltage input when in analog mode. access to counter/timers 1 is made through p31 (t in ) and p36 (t out ). handshake lines for ports 0 and 2 are available on p31/p36 and p32/p35 (table 10). port 3 also provides the following control functions: hand- shake for ports 0 and 2 (/dav and rdy); three external in- terrupt request signals (irq2-irq0); timer input and out- put signals (t in and t out ). auto latch. the auto-latch instruction puts valid cmos levels on cmos inputs that are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. note: pins 03, 04, 05, 06 have permanently enabled auto latches. comparator inputs. port 3, p31 and p32, each have a comparator front end. the comparator reference voltage, p33, is common to both comparators. in analog mode, the p33 input functions as a reference voltage to the compar- ators. in analog mode, the internal p33 register and its cor- responding irq1 is connected to the stop-mode recovery source selected by the smr register. in this mode, any of the stop-mode recovery sources are used to toggle the p33 bit or generate irq1. in digital mode, p33 can be used as a port 3 register input or irq1 source. p34 out- puts the comparator outputs by software programming the pcon register bit d0 to 1. note : when enabling/or disabling the analog mode, the following is recommended: 1. allow two nop delays before reading the comparator output 2. disable interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. table 10. port 3 pin assignments pin i/o ctc1 analog int. p0 hs p2 hs p31 in t in an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 p34 out an1-out p35 out r/d p36 out t out r/d notes: hs = handshake signals d = /dav r = rdy
z86c83/c84/e83 cmos z8 mcu zilog 8-26 p r e l i m i n a r y ds97dz80700 pin functions (continued) figure 12. port 3 input conguration port 3 (i/o) port 3 p36 p35 p34 p33 p32 p31 d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) from stop-mode recovery source 1 = analog 0 = digital irq2, t in , p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an + - + -
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-27 1 port configuration register (pcon). the pcon config- ures the ports individually for comparator output on port 3. the pcon register is located in the expanded register file at bank f, location 00 (figure 13). bit 0 multiplexes comparator an1 output at p34. a "1" in this location brings the comparator output to p34 (figure 14), and a "0" puts p34 into its standard i/o config- uration. note: only comparator output an1 is multiplexed to a port 3 output. comparator an2 output is not connected to any pins. note that the pcon register is reset upon the occurrence of a wdt reset (not in stop mode), and power-on reset (por). figure 13. port conguration register (pcon) (write-only) figure 14. port 3 p34 output conguration d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34 standard output * 1 p34 comparator output reserved (must be 1) pcon (f) 00 * default setting from stop-mode recovery, power-on reset, and any wdt reset. 0 port 0 open-drain 1 port 0 push-pull* reserved (must be 1) p34 out p31 + - ref (p33) p34 pad pcon d0 * reset condition normal 0 p34 standard output 1 p34 comparator output * an1
z86c83/c84/e83 cmos z8 mcu zilog 8-28 p r e l i m i n a r y ds97dz80700 functional description reset. (input, active low). this pin initializes the mcu. reset is accomplished either through power-on reset (por), watch-dog timer (wdt) reset, or external reset. during por, and wdt reset, the internally generated re- set is driving the reset pin low for the por time. any de- vices driving the reset line must be open-drain to avoid damage from a possible conflict during reset conditions. pull-up is provided internally. after the por time, /reset is a schmitt-triggered input. after the reset is detected, an internal rst signal is latched and held for an internal register count of 18 exter- nal clocks, or for the duration of the external reset, which- ever is longer. program execution begins at location 000c (hex), 5-10 tpc cycles after the rst is released. for por, the reset output time is t por . program memory. c83/c84/e83/e84 can address up to 4 kb of internal program memory (figure 15). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that cor- respond to the six available interrupts. bytes 13 to 4095 consist of on-chip, mask-programmed rom. rom protect. the 4 kb of program memory is mask pro- grammable. a rom protect feature will prevent dumping of the rom contents from an external program outside the rom. expanded register file. the register file has been ex- panded to allow for additional system control registers and for mapping of additional peripheral devices and input/out- put ports into the register address area. the z8 register address space r0 through r15 is implemented as 16 groups of 16 registers per group (figure 16). these regis- ter banks are known as the expanded register file (erf). bits 3-0 of the register pointer (rp) select the active erf bank. bits 7-4 of register rp select the working register group (figure 16). four system configuration registers re- side in the erf address space in bank f and eight regis- ters reside in bank c. the rest of the erf addressing space is not physically implemented, and is open for future expansion. note: when using zilog's cross assembler version 2.1 or earlier, use the ld rp, #0x instruction rather than the srp #0x instruction to access the erf. figure 15. program memory map 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 2048/4096
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-29 1 figure 16. expanded register file architecture
z86c83/c84/e83 cmos z8 mcu zilog 8-30 p r e l i m i n a r y ds97dz80700 functional description (continued) register file. the register file consists of three i/o port registers, 237 general-purpose registers, 15 control and status registers, and four system configuration registers in the expanded register group (figure 16). the instruc- tions can access registers directly or indirectly through an 8-bit address field. this allows a short 4-bit register ad- dress using the register pointer (figure 18). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer (figure 17) addresses the starting loca- tion of the active working-register group. note: register bank e0-ef is only accessed either as working registers or through indirect addressing modes. caution: d4 of control register p01m (r251) must be 0. r254. the c83/c84/e83 has one extra general-purpose register located at feh (r254). stack. the c83/c84/e83 has an 8-bit stack pointer (r255) used for the internal stack that resides within the 236 general-purpose registers. register r254 cannot be used for stack. general-purpose registers (gpr). these registers are undefined after the device is powered up. the registers keep their last value after any reset, as long as the reset occurs in the v cc voltage-specified operating range. it will not keep its last state from a v lv reset if the v cc drops be- low 1.8v. this includes register r254. note: register bank e0-ef is only accessed either as working register or through indirect addressing modes. ram protect. the upper portion of the ram? address spaces %80f to %ef (excluding the control registers) are protected from writing. the user activates this feature from the internal rom code to turn off/on the ram protect by loading either a 0 or 1 into the interrupt mask (imr) regis- ter, bit d6. a 1 in d6 enables ram protect. figure 17. register pointer register d7 d6 d5 d4 d3 d2 d1 d0 expanded register group working register group rp r253 note: default setting after reset = 00000000 figure 18. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports* specified working register group the lower nibble of the register file address provided by the instruction points to the specified register. r3 r2 r1 r0 register group 1 register group 0* r15 to r0 r15 to r4* r3 to r0* r15 to r0 ff f0 0f 00 1f 10 2f 20 3f 30 4f 40 5f 50 6f 60 7f 70 * expanded register file bank (0) is selected in this figure by handling bits d3 to d0 as "0" in register r253 (rp).
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-31 1 counter/timers. there are two 8-bit programmable counter/timers (t0-t1), each driven by its own 6-bit pro- grammable prescaler. the t1 prescaler is driven by inter- nal or external clock sources; however, the t0 prescaler is driven by the internal clock only (figure 19). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when the counter reaches the end of the count, a timer interrupt re- quest, irq4 (t0) or irq5 (t1), is generated. the counters can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). the counters, but not the prescalers , are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and is either the inter- nal microprocessor clock divide-by-four, or an external sig- nal input through port 3. the timer mode register config- ures the external timer input (p31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. the counter/timers can be cascaded by connecting the t0 output to the input of t1. t in mode is enabled by setting r243 pre1 bit d1 to 0. figure 19. counter/timer block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ?6 ? 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register ? clock logic irq4 tout p36 irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock d0 (smr) ? ? osc d1 (smr)
z86c83/c84/e83 cmos z8 mcu zilog 8-32 p r e l i m i n a r y ds97dz80700 functional description (continued) interrupts. the z8 has six different interrupts from six dif- ferent sources. these interrupts are maskable, prioritized (figure 20) and the six sources are divided as follows: four sources are claimed by port 3 lines p33-p30, and two in counter/timers (table 11). the interrupt mask register globally or individually enables or disables the six interrupt requests. when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. an interrupt ma- chine cycle is activated when an interrupt request is granted. this action disables all subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that interrupt. figure 20. interrupt block diagram table 11. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, irq0 0, 1 external (p32), rise fall edge triggered irq1, irq1 2, 3 external (p33), fall edge triggered irq2 /dav2, irq2, t in 4, 5 external (p31), rise fall edge triggered irq3 irq3 6, 7 by user software irq4 t0 8, 9 internal irq5 t1 10, 11 internal interrupt edge select irq (d6, d7) irq1, 3, 4, 5 irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 irq2
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-33 1 all z8 interrupts are vectored through locations in the pro- gram memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 may be rising, falling, or both edge trig- gered, and are programmable by the user. the software may poll to identify the state of the pin. programming bits for the interrupt edge select is located in the irq register (r250), bits d7 and d6. the configu- ration is shown in table 12. clock. the z8 on-chip oscillator has a high-gain, parallel- resonant amplifier for connection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 16 mhz max., with a series resistance (rs) of less than or equal to 100 ohms when clocking from 1 mhz to 16 mhz. the crystal should be connected across xtal1 and xtal2 using the vendor's recommended capacitor values from each pin directly to the device ground pin to reduce ground noise injection into the oscillator (figure 21). note: for better noise immunity, the capacitors should be tied directly to the device ground pin (v ss ). table 12. irq register irq interrupt edge d7 d6 p31 p32 0 0 f f 0 1 f r 1 0 r f 1 1 r/f r/f notes: f = falling edge r = rising edge figure 21. oscillator conguration xtal1 xtal2 c1 c2 c1 c2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 22 pf typ * f = 8 mhz lc external clock l * preliminary value including pin parasitics * * device ground pin vss* * vss* * vss* * vss* *
z86c83/c84/e83 cmos z8 mcu zilog 8-34 p r e l i m i n a r y ds97dz80700 functional description (continued) analog-to-digital converter the analog-to-digital (adc) is an 8-bit half flash converter that uses two reference resistor ladders for its upper 4 bits (msbs) and lower 4 bits (lsbs) conversion. two reference voltage pins, av cc and a gnd , are provided for external reference voltage supplies. during the sampling period from one of the eight channel inputs, the converter is also being auto-zeroed before starting the conversion. the conversion time is dependent on the internal clock fre- quency. the minimum conversion time is 35 x sclk (see figure 22). the adc is controlled by the z8 and its three registers (two control and one result) are mapped into the extended register file. a conversion can be initiated by writing to the adc control register 0 after the adc control register 1 is configured. the start command is implemented in such a way as to be- gin a conversion at any time, if a conversion is in progress and a new start command is received, then the conversion in progress will be aborted and a new conversion will be initiated. this allows the programmed values to be changed without affecting a conversion-in-progress. the new values will take effect only after a new start command is received. the adc can be disabled (for low power) or enabled by a control register bit. though the adc will function for a smaller input voltage and voltage reference, the noise and offsets remain con- stant over the specified electrical range. the errors of the converter will increase and the conversion time may also take slightly longer due to smaller input signals. adc calibration offset specially matched resistors are program-enabled to allow 35 percent or 50 percent offset from a gnd . they may se- lectively enable these resistors to offset the a gnd by 50 percent (2.5v to 5v) or 35 percent (1.75v to 5v) thereby allowing the 8-bit adc across a narrower voltage range. this will allow significant resolution improvement within the reduced voltage range. note: the av cc must be the same value as v cc and a gnd must be the same value as gnd. figure 22. adc architecture start converter a/d control reg. 8 8 8 a/d result reg. a/d converter av cc a gnd a/d control reg. 8 selected channel ext sample and hold adc register 9 d4, d5 4 calibration offset adc0 adr1 adc1 vref + vcc vref- gnd
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-35 1 channel select (bits 2, 1, 0) * default after reset ade (bit 7). a zero powers down and disables power and any a/d conversions or accessing any adc registers ex- cept writing to ade bit. a one enables all adc accesses. adc result register is shown in figure 25. figure 23. adc control register 0 (read/write) scan 0 no action* 1 convert channel then stop csel2 csel1 csel0 channel 0 0 0 0 (p20)* 0 0 1 1 (p21) 0 1 0 2 (p22) 0 1 1 3 (p23) 1 0 0 4 (p24) 1 0 1 5 (p25) 1 1 0 6 (p26) 1 1 1 7 (p27) note: adco d4 must equal 1 to allow port bit as adc input. figure 24. adc control register 1 (read/write) d7 d6 d5 d4 d3 d2 d1 d0 csel0 csel1 csel2 adc0 (a) bank c, register 8 scan 0 = no action*. 1 = convert, then stop. a in /input/output control 0 = no action* 1 = enable selected channel (d 2 ,d 1 ,d 0 ) as analog input on associated port 20-27 must be d7 = 0 d6 = 0 d5 = 1 * default after reset d7 d6 d5 d4 d3 d2 d1 d0 adc1 bank c, register 9 ade 0 disable* 1 enable must be 0. d5 d4 0 0 50 % agnd offset 1 0 35% agnd offset 0 1 reserved 1 1 no offset reserved (must be 1) * default after reset figure 25. result register (read-only) figure 26. bank c data d7 d6 d5 d4 d3 d2 d1 d0 adr bank c, register a reg f reg e reg d reg c reg b reg a reg 9 reg 8 ad control 0 reg 7 reg 6 reg 5 reg 4 reg 3 reg 2 reg 1 reg 0 ad control 1 ad result 1 these registers can be accessed.
z86c83/c84/e83 cmos z8 mcu zilog 8-36 p r e l i m i n a r y ds97dz80700 functional description (continued) figure 27 shows the input circuit of the adc. when con- version starts the analog input voltage is connected to the msb and lsb flash converter inputs as shown in the input impedance ckt diagram. effectively, shunting 31 parallel internal resistance of the analog switches and simulta- neously charging 31 parallel 0.5 pf capacitors, which is equivalent to seeing a 400 ohms input impedance in par- allel with a 16 pf capacitor. other input stray capacitance adds about 10 pf to the input load. for input source resis- tances up to 2 kohms can be used under normal operating condition without any degradation of the input settling time. for larger input source resistance, increasing conversion cycle time or adding a capacitor to the input may be re- quired to compensate the input settling time problem. typical z8 a/d conversion sequence 3. set the register pointer to extended bank (c), that is, srp #%0c instruction. 4. next, set ade flag by loading adc1 control register bank (c) register 9, bit 7. also, load bits 0-4 of this same register to select a av cc or a gnd offset value. a precision voltage divider connected to the a/d resistive ladder can offset conversion dynamic range to specified limits within the av cc and a gnd limits. by loading bank (c) register 9, bits 0-4, with the appropriate value it is possible to select from these groups: a. no offset. the converter dynamic range is from 0v to 5.0v for av cc = 5.0v. b. 35 percent a gnd offset. the converter dynamic range is 1.75v - 5.0v for av cc = 5.0v. c. 50 percent a gnd offset. the converter dynamic range is 2.5v - 5.0v for av cc = 5.0v. 5. select one of the eight a/d inputs for conversion by loading bank (c) register 8 with the desired attributes: bits 0 - 2 select an a/d input, bits 3 and 4 select a/d conversion (or digital port i/o). 6. set bank (c) register 8, bit 3 to enable a/d conversion. (this flag can be set concurrently with step 3.) this flag is automatically reset when the a/d conversion is completed, so a bit test can be performed to determine a/d readiness if necessary. 7. read the a/d result in bank (c) register a. please note that the a/d result is not valid (indeterminate) unless ade flag (register 9, bit 7) was previously set, otherwise a/d converter output is tri-stated. figure 27. input impedance of adc cmos switch on resistance 2 - 5 k w c parasitic r source c .5 pf v ref c .5 pf c .5 pf 31 cmos digital comparators
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-37 1 digital-to-analog converters the z86c84 has two digital-to-analog converters (dacs). each dac is an 8-bit resistor string, with a pro- grammable 0.25x, 0.5x, or 1x gain output buffer. the dac output voltage settles after the internal data is latched into the dac data register. the top and bottom ends of the resistor ladder are register-selected to be connected to ei- ther the analog supply rails, av cc and a gnd , or two exter- nally-provided reference voltages, vdhi and vdlo. exter- nal references are recommended to explicitly set the dac output limits. since the gain stage cannot drive to the sup- ply rails, vdhi and vdlo must be within ranges shown in the specifications. if either reference approaches the ana- log supply rails, the output will be unable to span the refer- ence voltage range. the externally provided reference voltages should not exceed the supply voltages. the dac outputs are latch-up protected and can drive output loads (figure 28). note: the av cc must be the same value as v cc and a gnd must be the same value as gnd figure 28. dac block diagram programmable gain data bus 8-bit resistor ladder 8 8 dacn data register dacrn control register 8 analog + - avcc dac1 or dac2 * bits 0, 1 agnd pad pad vdlo high pad vdhi note: * dacrn control register bits low (n = 1 or 2)
z86c83/c84/e83 cmos z8 mcu zilog 8-38 p r e l i m i n a r y ds97dz80700 functional description (continued) the d/a conversion for dac1 is driven by writing 8-bit data to the dac1 data register (bank c, register 06h). the d/a conversion for dac2 is controlled by the dac2 data register (bank c, register 07h). each dac data register is initialized to midrange 80h on power-up. there are two dac control registers: dacr1 (bank c, register 04h) for dac1, and dacr2 (bank c, register 05h) for dac2. control register bits 0 and 1 set the dac gain. when dac data is 80h, the dac output is constant for any gain setting (figure 29 and figure 31). figure 29. d/a 1 control register figure 30. d/a 1 data register d7 d6 d5 d4 d3 d2 d1 d0 dac1 gain 0 0 1 x 0 1 1/2 x 1 0 1 not used 1 1 1/4 x dacr1 bank c, register 4 dac1 enable 0 disable 1 enable reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 dac1 bank c, register 6 0 = low level 1 = high level figure 31. d/a 2 control register figure 32. d/a 2 data register d7 d6 d5 d4 d3 d2 d1 d0 dac2 gain 0 0 1 x 0 1 1/2 x 1 0 1 not used 1 1 1/4 x dacr2 bank c, register 5 dac2 enable (must be 0 for c83) 0 disable 1 enable reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 dac2 bank c, register 7 0 = low level 1 = high level
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-39 1 power-on reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator or by the xtal oscillator is used for the por timer function. the por time allows v cc and the oscillator circuit to stabilize before instruction exe- cution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: n power fail to power ok status n stop-mode recovery (if d5 of smr register = 1) n wdt time-out (including from stop mode) the por time is t por minimum. bit 5 of the stop mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock and lc oscillators with fast start up time). halt. turns off the internal cpu clock but not the xtal oscillation. the counter/timers and external interrupts irq0, irq1, and irq2 remain active. the device is recov- ered by interrupts, either externally or internally generated (a por or a wdt time-out). an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. in case of a por or a wdt time-out, pro- gram execution will restart at address 000ch. stop. this instruction turns off the internal clock and ex- ternal crystal oscillation and reduces the standby current to 10 ? (typical) or less. the stop mode is terminated by a reset of either wdt time-out, por, or stop-mode re- covery. this causes the processor to restart the applica- tion program at address 000ch. figure 33. gain control on dac 3.5 3.05 2.6 2.15 2% accuracy 1.7 1.26 .8vdlo 0 80h ffh 3.5v vdhi 1/4x 1/2x 1x dac output in volts 2.15 dac data register value notes: vcc = 5.0v ?0% vdhi = 3.5v vdlo = 0.8v
z86c83/c84/e83 cmos z8 mcu zilog 8-40 p r e l i m i n a r y ds97dz80700 in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. to do this, the user must execute a nop (opcode = ffh) immediately before the appropri- ate sleep instruction, that is , stop-mode recovery (smr) register. this register se- lects the clock divide value and determines the mode of stop-mode recovery (figure 34 and figure 35). all bits are write-only, except bit 7, which is read-only. bit 7 is a flag bit that is hardware set on the condition of stop re- covery and reset by a power-on cycle. bit 6 controls wheth- er a low level or a high level is required from the recovery source. bit 5 controls the reset delay after recovery. bits 2, 3, and 4, or the smr register, specify the source of the stop-mode recovery signal. bits 0 and 1 determine the time-out period of the wdt. the smr register is located in bank f of the expanded register group at address 0bh. when the stop-mode recovery sources are selected in this register, then smr2 register bits d0,d1 must be set to 0. sclk/tclk divide-by-16 select (d0). d0 of the smr controls a divide-by-16 prescaler of sclk/tclk. the con- trol selectively reduces device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). this bit is reset to d0 = 0 after a stop-mode recov- ery, wdt time-out, and por. external clock divide-by-two (d1). this bit can elimi- nate the oscillator divide-by-two circuitry. when this bit is 0, the system clock (sclk) and timer clock (tclk) are equal to the external clock halt mode frequency divided by two. the sclk/tclk is equal to the external clock fre- quency when this bit is set (d1=1). using this bit together with d7 of pcon further helps lower emi (that is, d7 (pcon) = 0, d1 (smr) = 1). the default setting is zero. maximum external clock frequency is 8 mhz when smr bit d1 = 1 where sclk/tclk = xtal. ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode figure 34. stop-mode recovery register (write-only except bit d7, which is read-only) d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0b sclk/tclk divide-by-16 0 off* * 1 on stop-mode recovery source 000 por only and/or external reset* 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on stop recovery level 0 low * 1 high stop flag (read-only) 0 por 1 stop recovery note: not used in conjunction with smr2 source * default setting after reset ** default setting after reset and stop-mode recovery * * external clock divide-by-2 0 sclk/tclk = xtal/2* 1 sclk/tclk = xtal figure 35. stop-mode recovery register 2 ([0f] dh: write-only) figure 36. sclk circuit d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) dh note: not used in conjunction with smr source stop-mode recovery source 2 00 por only* 01 and p20,p21,p22,p23 10 and p20,p21,p22,p23, p24,p25,p26,p27 reserved (must be 0) smr, d0 2 16 osc sclk tclk smr, d1
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-41 1 stop-mode recovery source (d2, d3, and d4). these three bits of the smr register specify the wake-up source of the stop recovery (figure 37 and table 13). when the stop-mode recovery sources are selected in this register then smr2 register bits d0,d1 must be set to zero. p33- p31 and port 2 cannot wake up from stop mode if the in- put lines are configured as analog inputs to the analog comparator or analog-to-digital converter. note: if the port 2 pin is configured as an output, this output level will be read by the smr circuitry. stop-mode recovery delay select (d5). this bit, if high, enables the t por /reset delay after stop-mode recov- ery. the default configuration of this bit is "1". a por or wdt reset will override the selection and cause the reset delay to occur. stop-mode recovery edge select (d6). a "1" in this bit position indicates that a high level on the output to the ex- clusive or-gate input from the selected recovery source wakes the z86c83/c84/e83 from stop mode. a "0" indi- cates low-level recovery. the default is 0 on por. this bit is used for either smr or smr2. cold or warm start (d7). this bit is set by the device upon entering stop mode. a 0 in this bit (cold) indicates that the device resets by por/wdt reset. a "1" in this bit (warm) indicates that the device awakens by a stop-mode recovery source. note: a wdt reset out of stop mode will also set this bit to a "1". stop-mode recovery register 2 (smr2). this register contains additional stop-mode recovery sources. when the stop-mode recovery sources are selected in this reg- ister then smr register bits d2, d3, and d4 must be 0. table 13. stop-mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 0 0 1 reserved 0 1 0 p31 transition (not in analog mode) 0 1 1 p32 transition (not in analog mode) 1 0 0 p33 transition (not in analog mode) 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 table 14. stop-mode recovery source smr:10 operation d1 d0 description of action 0 0 por and/or external reset recovery 0 1 logical and of p20 through p23 1 0 logical and of p20 through p27 figure 37. stop-mode recovery source p31 p32 p33 p27 stop-mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) to p33 data latch and irq1 to por /reset 0 1 0 0 1 1 mux d4 d3 d2 1 1 0 d4 d3 d2 1 1 1 p20 p23 p20 p27 smr2 smr2 p20 p23 p20 p27 vdd smr2 vdd smr d4 d3 d2 0 0 d1 d0 1 0 d1 d0 d1 d0 1 0 0 0 smr smr d4 d3 d2 1 0 1 smr d4 d3 d2 d4 d3 d2 smr 1 0 0 0 smr
z86c83/c84/e83 cmos z8 mcu zilog 8-42 p r e l i m i n a r y ds97dz80700 watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction and refreshed on subse- quent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the por clock source is selected with bit 4 of the wdt register (figure 38). wdt instruction affects the z (zero), s (sign), and v (overflow) flags. the wdtmr must be written to within 64 internal system clocks. after that, the wdtmr is write pro- tected. note: wdt time-out while in stop-mode will not reset smr, pcon, wdtmr, p2m, p3m, ports 2 and 3 data registers, but will cause the reset delay to occur. the power-on reset (por) clock source is selected with bit 4 of the wdtmr. bits 0 and 1 control a tap circuit that determines the time-out period. bit 2 determines whether the wdt is active during halt and bit 3 determines wdt activity during stop. if bits 3 and 4 of this register are both set to "1," the wdt is only driven by the external clock dur- ing stop mode. this feature makes it possible to wake up from stop mode from an internal source. bits 5 through 7 of the wdtmr are reserved (figure 39). this register is accessible only during the first 60 processor cycles (60 sclks) from the execution of the first instruction after power-on-reset, watch-dog reset or a stop-mode re- covery. after this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank f of the expanded register group at address location 0fh. figure 38. resets and wdt clk 18 clock reset generator reset /clear wdt tap select on board rc osc. ck /clr 128 sclk por 256 sclk 512 sclk 1024 sclk 4096 sclk 3.0v operating voltage det. internal /reset wdt select (wdtmr) ck source select (wdtmr) xtal vcc vlv from stop mode recovery source /wdt stop delay select (smr d5) 12 ns glitch filter + - wdt/por counter chain m u x /reset
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-43 1 wdt time select (d1, d0). selects the wdt time-out pe- riod. it is configured as shown in table 15. wdt during halt (d2). this bit determines whether or not the wdt is active during halt mode. a "1" indicates active during halt. the default is "1". note: if wdt is permanently selected (always on mode), the wdt will continue to run even if set not to run in stop or halt mode. wdt during stop (d3). this bit determines whether or not the wdt is active during stop mode. since xtal clock is stopped during stop mode, unless as specified below, the on-board rc has to be selected as the clock source to the por counter. a "1" indicates active during stop. the default is "1". if bits d3 and d4 are both set to "1", the wdt only, is driven by the external clock during stop mode. notes: 1. if wdt is permanently selected (always on mode) using internal on-board rc oscillator, the wdt will continue to run even if set not to run in stop or halt mode. 2. wdt instructions affect the z (zero), s (sign), and v (overflow) flags. on-board, power-on-reset rc or external xtal1 oscillator select (d4). this bit determines which oscilla- tor source is used to clock the internal por and wdt counter chain. if the bit is a "1", the internal rc oscillator is bypassed and the por and wdt clock source is driven from the external pin, xtal1. the default configuration of this bit is 0, which selects the rc oscillator. if the xtal1 pin is selected as the oscillator source for the wdt, during stop mode, the oscillator will be stopped and the wdt will not run. this is true even if the wdt is selected to run during stop mode. v cc voltage comparator. an on-board voltage compar- ator checks that v cc is at the required level to ensure cor- rect operation of the device. reset is globally driven if v cc is below the specified voltage (typically 2.6v). rom protect. rom protect is mask or otp bit-program- mable. it is selected by the customer at the time the rom code is submitted. rom mask selectable options there are two rom mask options that must be selected at the time the rom mask is ordered (rom code submitted) for the z86c83/c84 and three Z86E83 otp bit options. figure 39. watch-dog timer mode register (write only) table 15. wdt time select (min. @ 5.0v) d1 d0 time-out of internal rc osc time-out of sclk clock 0 0 6.25 ms min 256 sclk 0 1 12.5 ms min 512 sclk 1 0 25 ms min 1024 sclk 1 1 100 ms min 4096 sclk note: the minimum time shown is for v cc @ 5.0v. d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap 00 256 sclk 01 512 sclk 10 1024 sclk 11 4096 sclk wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset ? xtal=sclk/tclk shown * * * table 16. selectable options option selection permanent wdt yes/no rom protect yes/no eprom/test mode disable* yes/no note: *for Z86E83 only eprom/test mode disable - on the Z86E83, the user can per- manently disable entry into eprom mode and test mode by programming this bit.
z86c83/c84/e83 cmos z8 mcu zilog 8-44 p r e l i m i n a r y ds97dz80700 expanded register file control registers (0c) figure 40. adc control register 0 (read/write) figure 41. adc control register 1 (read/write) figure 42. ad result register (read only) d7 d6 d5 d4 d3 d2 d1 d0 adc0 bank c, 8h scan 0 = no action* 1 = convert channel then stop a in /input/output control 0 = no action (digital function)* 1 = enable selected channel (m 2 , m 1 , m 0 ) as analog input on associated port p27-p20 channel select (bits 2,1,0) csel2 0 0 0 0 1 1 1 1 csel1 0 0 1 1 0 0 1 1 csel0 0 1 0 1 0 1 0 1 channel 0* 1 2 3 4 5 6 7 * default setting after reset. must be 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 adc1 bank c, register 9 ade 0 disable* 1 enable must be 0. d5 d4 0 0 50 % agnd offset 1 0 35% agnd offset 0 1 reserved 1 1 no offset reserved (must be 1.) d7 d6 d5 d4 d3 d2 d1 d0 adr1 bank c, ah data figure 43. d/a 1 control register figure 44. d/a 2 control register figure 45. d/a 1 data register figure 46. d/a 2 data register d7 d6 d5 d4 d3 d2 d1 d0 dac1 gain 0 0 1 x 0 1 1/2 x 1 0 1 not used 1 1 1/4 x dacr1 bank c, register 4 dac1 enable (must be 0 for z86c83) 0 disable 1 enable reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 dac2 gain 0 0 1 x 0 1 1/2 x 1 0 1 not used 1 1 1/4 x dacr2 bank c, register 5 dac2 enable (must be 0 for c83) 0 disable 1 enable reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 dac1 bank c, register 6 0 = low level 1 = high level d7 d6 d5 d4 d3 d2 d1 d0 dac2 bank c, register 7 0 = low level 1 = high level
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-45 1 expanded register file control registers figure 47. stop-mode recovery register (write-only, except bit 7 which is read-only) figure 48. watch-dog timer mode register 2 d7 d6 d5 d4 d3 d2 d1 d0 smr (f) 0b sclk/tclk divide-by-16 0 off * * 1 on stop-mode recovery source 000 por only and/or external reset* 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on* stop recovery level 0 low* 1 high stop flag (read only) 0 por* 1 stop recovery note: not used in conjunction with smr2 source * default setting after reset. * * default setting after reset and stop-mode recovery. external clock divide by 2 0 sclk/tclk =xtal/2* 1 sclk/tclk =xtal d7 d6 d5 d4 d3 d2 d1 d0 smr2 (f) dh note: not used in conjunction with smr source stop-mode recovery source 2 00 por only* 01 and p20,p21,p22,p23 10 and p20,p21,p22,p23, p24,p25,p26,p27 reserved (must be 0) 11 reserved figure 49. watch-dog timer mode register (write-only) figure 50. port conguration register (pcon) (write-only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap 00 256 sclk 01 512 sclk 10 1024 sclk 11 4096 sclk wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset ? xtal=sclk/tclk shown * * * d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34 standard output * 1 p34 comparator output reserved (must be 1) pcon (f) 00 * default setting from stop-mode recovery power-on reset, and any wdt reset. 0 port 0 open-drain 1 port 0 push-pull* reserved (must be 1) 0 = low emi osc 1 = standard osc
z86c83/c84/e83 cmos z8 mcu zilog 8-46 p r e l i m i n a r y ds97dz80700 z8 control registers figure 51. reserved figure 52. timer mode register (f1 h : read/write) figure 53. counter/timer 1 register (f2 h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) r240 d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count tin modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) tout modes 00 not used 01 t0 out 10 t1 out 11 internal clock out r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 t initial value (when written) (range: 1-256 decimal 01-00 hex) t current value (when read) 1 1 r242 t1 figure 54. prescaler 1 register (f3 h : write-only) figure 55. counter/timer 0 register (f4 h : read/write) figure 56. prescaler 0 register (f5 h : write-only) figure 57. port 3 mode register (f7 h : write-only) d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1internal 0 t1external timing input (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when written) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r244 t0 0 t0 single pass 1 t0 modulo n d7 d6 d5 d4 d3 d2 d1 d0 count mode reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0 d7 d6 d5 d4 d3 d2 d1 d0 0 port 2 open-drain* 1 port 2 push-pull port 3 inputs 0 digital* 1 analog reserved (must be 0) r247 p3m *default setting after reset
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-47 1 figure 58. port 2 mode register (f6 h : write-only) figure 59. port 0 and 1 mode register (f8 h : write-only) figure 60. interrupt priority register (f9 h : write-only) d7 d6 d5 d4 d3 d2 d1 d0 p27- p20 i/o definition 0 defines bit as output 1 defines bit as input* r246 p2m *default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 p00-p03 mode ? 00 output 01 input 1x a11-a8 r248 p01m reserved (must be 1) reserved (must be 0) p04-p06 mode 00 output 01 input 1x a15-a12 d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved (must be 0) r249 ipr figure 61. interrupt request register (f ah : read/write) figure 62. interrupt mask register (f bh : read/write) figure 63. flag register (f ch : read/write) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = software controlled irq4 = t0 irq5 = t1 inter edge 00 p31 01 p31 10 p31 - 11 p31 - r250 irq default setting after reset = 00h p32 p32 - p32 p32 - d7 d6 d5 d4 d3 d2 d1 d0 1 ram protect enabled 0 ram protect disabled * 1 enables irq5-irq0 (d0 = irq0) 1 enables interrupts 0 disable interrupts * (default setting after reset.) r251 imr d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag r252 flags
z86c83/c84/e83 cmos z8 mcu zilog 8-48 p r e l i m i n a r y ds97dz80700 z8 control registers (continued) figure 64. register pointer (f dh : read/write) figure 65. general-purpose register (f eh : read/write) d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer r253 rp default setting after reset = 00h d7 d6 d5 d4 d3 d2 d1 d0 r254 gpr 0 = low level 1 = high level figure 66. stack pointer (f fh : read/write) figure 67. port 2 pull-up register d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp7-sp0) r255 spl 0 = low level 1 = high level d7 d6 d5 d4 d3 d2 d1 d0 port 2 (p27-p20) 10k pull-up 0 = disabled 1 = enabled p2res bank c, register 3
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-49 1 package information figure 68. 28-pin dip package diagram figure 69. 28-pin soic package diagram
z86c83/c84/e83 cmos z8 mcu zilog 8-50 p r e l i m i n a r y ds97dz80700 package information (continued) figure 70. 28-pin plcc package diagram
z86c83/c84/e83 zilog cmos z8 mcu ds97dz80700 p r e l i m i n a r y 8-51 1 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part desired. codes package p = plastic dip s = plastic soic temperature s = 0? to + 70? e = -40? to +105? speed 16 = 16 mhz environmental c = plastic standard z86c83 16 mhz Z86E83 16 mhz 28-pin dip 28-pin soic 28-pin plcc 28-pin dip 28-pin soic 28-pin plcc z86c8316psc z86c8316ssc z86c8316vsc Z86E8316psc Z86E8316ssc Z86E8316vsc z86c8316pec z86c8316sec z86c8316vec Z86E8316pec Z86E8316sec Z86E8316vec z86c84 16 mhz 28-pin dip 28-pin soic 28-pin plcc z86c8416psc z86c8416ssc z86c8416vsc z86c8416pec z86c8416sec z86c8416vec example: z 86c83 16 p s c environmental flow temperature package speed product number zilog prefix is a z86c83, 16 mhz, dip, 0? to +70?, plastic standard flow
z86c83/c84/e83 cmos z8 mcu zilog 8-52 p r e l i m i n a r y ds97dz80700 ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056

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